Memory architectures, particularly dynamic random access memory (DRAM) architectures currently exist for sizes up to 16 megabits. However, until now, no memory architecture has existed that is well suited for the next generations of memory of 64 megabits and beyond.
FIG. 1 illustrates a memory array architecture featuring grouped input/output lines (input/output also referred to as I/O). FIG. 1 illustrates one 512,000 bit memory array (hereinafter referred to as a 512k array) and its associated circuitry, being generally referenced at 2. One section of the array and its associated circuitry, out of 256 sections, consisting of circuitry, bound by the rectangular box and generally indicated by 4 is show, enlarged to facilitate discussion. The 512k array is associated with a pair of sense amplifier groups. Each group comprises 1024 sense amplifiers. One sense amplifier from each group is included within enlarged section 4 with each sense amplifier (also called sense amp) being labeled S/A. The remaining 1023 sense amplifiers in each group are generally labeled 1k S/A. Each vertical row (indicated along the directions of arrows v) of sense amplifiers can service two 512k arrays of memory. Bit lines, generally indicated at 6, are of the twisted type (each twisted pair comprising true and complement signals) and connect to two sense amplifiers from each 512k array. Therefore, each sense amplifier is connected to 4 bit lines as shown. However, note that since only one 512k array is shown, a pair of bit line connections for each sense amplifier is truncated along an outer edge for the other 512k array. For operation upon a memory cell, Y decoder 8 or as it is sometimes called, a column decoder, enables selection for at least one column of memory cells. Row decoder 10 selects the row of memory cells. The transmission media from row decoder 10 are word lines. As shown, one extended arrow 11 from row decoder 10 indicates word line selection by row decoder 10. An extended arrow 9 from Y decoder 8 represents column selection by Y decoder 8. Note that the vicinity of the intersection of a word line and a bit line can be equated to the location of a memory cell in the 512k array. After selection of a memory cell as a result of row and column selection by row decoder 10 and Y decoder 8, respectively, up to 4 pairs of input/output data can be sent to or received from the main input/output lines 24 from each group of sense amplifiers, hence, the term 11 grouped input/output lines 11. Pairs of data refers to true and complemented data. Consequently, up to 8 pairs of input/output data can be sent to or received from the main input/output lines from both groups of sense amplifiers per operating cycle.
With regard to the layout of the grouped input/output lines memory array architecture, 4 input/output line pairs fit within a sense amplifier pitch. A random logic layout for comparators exists for parallel testing of the memory.
If this architecture is adapted for use in a 64 megabit memory, 128 sets of the 512k array are needed. Therefore, sense amplifier activation is determined by the row decoder 10 for each 512k array. Consequently, 2048 sense amplifiers are activated per word line per 512k array. 64 bits of parallel testing is permitted with this memory adapted for 64 megabit use. Thus 128 bits can be tested simultaneously which results in 256 word lines being activated. A direct connection from sense amplifier to an associated input/output line exists. Consequently, a large capacitance exists on each input/output line since there are 256 word sense amplifiers per input/output. The major drawback of this architecture for adaptation to a 64 megabit memory is that out of so much available data, only a small portion can be selected at a time. Such poor selectivity is not suitable for good 64 megabit memory operation.
FIG. 2 illustrates a multiple input/output lines array architecture. FIG. 2 illustrates one 512,000 bit memory array and its associated circuitry, being generally referenced at 2. One section of the array and its associated circuitry out of 256 sections consisting of circuitry bound by the rectangular box and generally indicated by 4 is shown enlarged to facilitate discussion. The 512k array is associated with a pair of sense amplifier groups. Each group comprises 1024 sense amplifiers. One sense amplifier from each group is included within enlarged section 4 with each sense amplifier being labeled S/A. The remaining 1023 sense amplifiers in each group are generally labeled 1k S/A. Each vertical row (indicated along the directions of arrows v) of sense amplifiers can service two 512k arrays of memory. Bit lines, generally indicated at 6, are of the twisted type (each twisted pair comprising true and complement signals) and connect to two sense amplifiers from each 512k array. Therefore, each sense amplifier is connected to 4 bit lines as shown. However, note that since only one 512k array is shown, a pair of bit line connections for each sense amplifier is truncated along an outer edge for the other 512k array. Each sense amplifier can be connected directly to a pair of local input/output lines, shown as LOCAL I/O and LOCAL I/O.sub.-- lines. A pair of of these local input/output lines exists for each sense amplifier. The connection to the sense amplifiers by the local input/output lines are shown as dots. As with the grouped input/output lines architecture, row decoder 10 selects the row of memory cells. Each pair of bit lines 6 in a selected 512k array either transmits a data signal to, or receives a data signal from a sense amplifier S/A. This information is either sent to or received from wide data path circuitry 22. Thus, at this stage, 1024 sense amplifiers (selected alternately out of 2 groups of sense amplifiers) either send information to or receive information from wide data path circuitry 22. Consequently, 1024 input/output line pairs are activated per operating cycle per 512k array. Thus, this architecture has high active power dissipation. Column selection occurs in connection with the activation of local input/output lines and sense amplifiers, whereby information sent to or received by wide data path circuitry 22 is selected by Y decoder 8. Y decoder 8 selects 8 pairs of data from the 1024 pairs of data received from 1024 sense amplifiers to place on the 8 pairs of main input/output lines 24. Pairs of data is a term referring to true and complemented data.
Adaptation of this multiple input/output lines memory array architecture for a 64 megabit memory requires sense amplifier activation determined by the row decoder. Thus, 2048 sense amplifiers are activated per word line per 512k array. Since a direct connection exists, from a sense amplifier to input/output lines, the lines are capacitance dominated. 1024 bits per word line parallel testing is provided by this multiple input/output lines memory array architecture.
This architecture is not well suited for a memory size of 64 megabits or greater. Particularly, the high active power dissipation caused by the 1024 input/output line pairs activated per operating cycle per 512k array is undesirable in a 64 megabit memory array architecture.